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a25l80p 8 mbit, low voltage, serial flash memory preliminary with 50 mhz spi bus interface preliminary (may, 2005, version 0.0) amic technology corp. document title 8 mbit, low voltage, serial flash memory with 50mhz spi bus interface revision history rev. no. history issue date remark 0.0 initial issue may 30, 2005
a25l80p 8 mbit, low voltage, serial flash memory preliminary with 50 mhz spi bus interface preliminary (may 2005, version 0.0) 1 amic technology corp. features 8 mbit of flash memory flexible sector architecture (4/4/8/16/32)kb/64x15 kb bulk erase (8 mbit) in 10s (typical) sector erase (512 kbit) in 1s (typical) page program (up to 256 bytes) in 3ms (typical) 2.7 to 3.6v single supply voltage spi bus compatible serial interface 50mhz clock rate (maximum) deep power-down mode 1a (typical) electronic signature - jedec standard (13h) general description the a25l80p is an 8 mbit (1m x 8) serial flash memory, with advanced write protection mechanisms, accessed by a high speed spi-compatible bus. the memory can be programmed 1 to 256 bytes at a time, using the page program instruction. the memory is organized as 16 sectors, each containing 256 pages. each page is 256 bytes wide. thus, the whole memory can be viewed as consisting of 4096 pages, or 1,048,576 bytes. the whole memory can be erased using the bulk erase instruction, or a sector at a time, using the sector erase instruction. pin configurations so8 connections so16 connections v cc c du q s hold v ss 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 a25l80p v cc c q d s w hold v ss 1 8 2 7 3 6 4 5 a25l80p du du du d du du du du w note: du = do not use
a25l80p preliminary (may 2005, version 0.0) 2 amic technology corp. block diagram control logic high voltage generator i/c shift register address register and counter 256 byte data buffer status register x decoder 256 byte (page size) y decoder size of the read-only memory area d q c 000ffh 00000h hold w s fffffh pin descriptions pin no. description c serial clock d serial data input q serial data output s chip select w write protect hold hold vcc supply voltage vss ground logic symbol a25l80p q d s w hold v ss v cc c
a25l80p preliminary (may 2005, version 0.0) 3 amic technology corp. signal description serial data output (q). this output signal is used to transfer data serially out of the device. da ta is shifted out on the falling edge of serial clock (c). serial data input (d). this input signal is used to transfer data serially into the device. it rece ives instructions, addresses, and the data to be programmed. valu es are latched on the rising edge of serial clock (c). serial clock (c). this input signal provides the timing of the serial interface. instructions , addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). chip select ( s ). when this input signal is high, the device is deselected and serial data out put (q) is at high impedance. unless an internal program, er ase or write status register cycle is in progress, the devic e will be in the standby mode (this is not the deep power-down mode). driving chip select ( s ) low enables the device, plac ing it in the active power mode. after power-up, a falling edge on chip select ( s ) is required prior to the start of any instruction. hold ( hold ). the hold ( hold ) signal is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the device must be selected, with chip select ( s ) driven low. write protect ( w ). the main purpose of this input signal is to freeze the size of the area of me mory that is protected against program or erase instructions (as specified by the values in the bp2, bp1 and bp0 bits of the status register). spi modes these devices can be driven by a microcontroller with its spi peripheral running in either of the two following modes: ? cpol=0, cpha=0 ? cpol=1, cpha=1 for these two modes, input data is latched in on the rising edge of serial clock (c), and output dat a is available from the falling edge of serial clock (c). the difference between the two modes, as shown in figure 2, is the clock polarity when the bus master is in stand-by mode and not transferring data: ? c remains at 0 for (cpol=0, cpha=0) ? c remains at 1 for (cpol=1, cpha=1)
a25l80p preliminary (may 2005, version 0.0) 4 amic technology corp. figure 1. bus master and memory devices on the spi bus bus master (st6, st7, st9, st10, other) spi interface with (cpol, cpha) = (0, 0) or (1, 1) cs3 cs2 cs1 spi memory device cqd s w hold spi memory device cqd s w hold spi memory device cqd s w hold sdi sdo sck note: the write protect ( w ) and hold ( hold ) signals should be driven, high or low as appropriate. figure 2. spi modes supported msb msb c c d q 00 1 1 cpol cpha
a25l80p preliminary (may 2005, version 0.0) 5 amic technology corp. operating features page programming to program one data byte, two in structions are required: write enable (wren), which is one byte, and a page program (pp) sequence, which consists of f our bytes plus data. this is followed by the internal program cycle (of duration t pp ). to spread this overhead, the page program (pp) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory. sector erase and bulk erase the page program (pp) instruction allows bits to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved, a sector at a time, using the sect or erase (se) instruction, or throughout the entire memory, using the bulk erase (be) instruction. this starts an inte rnal erase cycle (of duration t se or t be ). the erase instruction must be preceded by a write enable (wren) instruction. polling during a write, program or erase cycle a further improvement in the ti me to write status register (wrsr), program (pp) or erase (se or be) can be achieved by not waiting for the worst case delay (t w , t pp , t se , or t be ). the write in progress (wip) bit is pr ovided in the status register so that the application program c an monitor its value, polling it to establish when the previous write cycle, program cycle or erase cycle is complete. active power, stand-by power and deep power-down modes when chip select ( s ) is low, the device is enabled, and in the active power mode. when chip select ( s ) is high, the device is disabled, but could remain in the active power mode until all internal cycles have completed (program, erase, write status register). the device then goes in to the stand-by power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the specific instruction (the enter deep power-down mode (dp) instruction) is executed. the device cons umption drops further to i cc2 . the device remains in this mode unt il another specific instruction (the release from deep power-down mode and read electronic signature (res) in struction) is executed. all other instructions are ignor ed while the device is in the deep power-down mode. this can be used as an extra software protection mechanism, when the device is not in active use, to protect the dev ice from inadvertent write, program or erase instructions. status register the status register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. wel bit. the write enable latch (wel) bit indicates the status of the internal write enable latch, bp2, bp1, and bp0 bits. the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. srwd bit. the status register writ e disable (srwd) bit is operated in conjunction with the write protect ( w ) signal. the status register write disable (srwd) bit and write protect ( w ) signal allow the device to be put in the hardware protected mode. in this mode, the non-volatile bits of the status register (srwd, bp 2, bp1, bp0) become read-only bits. protection modes the environments where non-volatile memory devices are used can be very noisy. no spi device can operate correctly in the presence of excessive noi se. to help combat this, the a25l80p boasts the following data protection mechanisms: power-on reset and an internal timer (t puw ) can provide protection against inadvertant changes while the power supply is outside the oper ating specification. program, erase and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. all instructions that modify data must be preceded by a write enable (wren) instruct ion to set the write enable latch (wel) bit. this bit is retu rned to its reset state by the following events: - power-up - write disable (wrdi) instruction completion - write status register (wrsr) instruction completion - page program (pp) instruction completion - sector erase (se) instruction completion - bulk erase (be) instruction completion the block protect (bp2, bp1, bp0) bits allow part of the memory to be configured as read- only. this is the software protected mode (spm). the write protect ( w ) signal allows the block protect (bp2, bp1, bp0) bits and status regi ster write disable (srwd) bit to be protected. this is the hardware protected mode (hpm). in addition to the low power c onsumption feature, the deep power-down mode offers extra software protection from inadvertant write, program a nd erase instructions, as all instructions are ignored exc ept one particular instruction (the release from deep power-down instruction).
a25l80p preliminary (may 2005, version 0.0) 6 amic technology corp. table 1. protected area sizes status register content memory content bp2 bit bp1 bit bp0 bit protected area unprotected area 0 0 0 none all sectors 1 (sixteen sectors: 0 to 15) 0 0 1 upper sixteenth (sector 15) lower fifteen-eighths (fifteen sectors: 0 to 14) 0 1 0 upper eighth (two sectors: 14 and 15) lower seven-eights (four teen sectors: 0 to 13) 0 1 1 upper quarter (four sectors: 12 to 15) lower three-quarters (twelve sectors: 0 to 11) 1 0 0 upper half (eight sectors: 8 to 15) lower half (eight sectors: 0 to 7) 1 0 1 all sectors (eight sectors: 0 to 15) none 1 1 0 all sectors (eight sectors: 0 to 15) none 1 1 1 all sectors (eight sectors: 0 to 15) none note: 1. the device is ready to accept a bulk erase instru ction if, and only if, all block protect (bp2, bp1, bp0) are 0. hold condition the hold ( hold ) signal is used to pause any serial communications with the device without resetting the clocking sequence. however, taking this signal low does not terminate any write status register, progr am or erase cycle that is currently in progress. to enter the hold condition, t he device must be selected, with chip select ( s ) low. the hold condition starts on the falling edge of the hold ( hold ) signal, provided that this coincides with serial clock (c) being low (as shown in figure 3.). the hold condition ends on the rising edge of the hold ( hold ) signal, provided that this coincides with serial clock (c) being low. if the falling edge does not coincide with serial clock (c) being low, the hold condition starts after serial clock (c) next goes low. similarly, if the rising edge does not coincide with serial clock (c) being low, the hold condition ends after serial clock (c) next goes low. this is shown in figure 3. during the hold condition, the serial data output (q) is high impedance, and serial data input (d) and serial clock (c) are don?t care. normally, the device is kept selected, with chip select ( s ) driven low, for the whole duration of the hold condition. this is to ensure that the stat e of the internal logic remains unchanged from the moment of enter ing the hold condition. if chip select ( s ) goes high while the device is in the hold condition, this has the effect of resetting the internal logic of the device. to restart communicati on with the device, it is necessary to drive hold ( hold ) high, and then to drive chip select ( s ) low. this prevents the device from going back to the hold condition. figure 3. hold condition activation hold condition (standard use) hold c hold condition (non-standard use)
a25l80p preliminary (may 2005, version 0.0) 7 amic technology corp. memory organization the memory is organized as: 1,048,576 bytes (8 bits each) 16 sectors (one (4/4/8/16/32) kbytes & 64x15 kbytes each) 4096 pages (256 bytes each). each page can be individually programmed (bits are programmed from 1 to 0). the device is sector or bulk erasable (bits are erased from 0 to 1) but not page erasable. table 2. memory organization sector sector size (kbytes) address range 15 64 f0000h fffffh 14 64 e0000h effffh 13 64 d0000h dffffh 12 64 c0000h cffffh 11 64 b0000h bffffh 10 64 a0000h affffh 9 64 90000h 9ffffh 8 64 80000h 8ffffh 7 64 70000h 7ffffh 6 64 60000h 6ffffh 5 64 50000h 5ffffh 4 64 40000h 4ffffh 3 64 30000h 3ffffh 2 64 20000h 2ffffh 1 64 10000h 1ffffh 0-4 32 08000h 0ffffh 0-3 16 04000h 07fffh 0-2 8 02000h 03fffh 0-1 4 01000h 01fffh 0-0 4 00000h 00fffh
a25l80p preliminary (may 2005, version 0.0) 8 amic technology corp. instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input (d) is sampled on the first rising edge of serial clock (c) a fter chip select ( s ) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (d), each bit being latched on the rising edges of serial clock (c). the instruction set is listed in table 3. every instruction sequence starts with a one-byte instruction code. depending on the instructi on, this might be followed by address bytes, or by data bytes, or by both or none. in the case of a read data bytes (read), read data bytes at higher speed (fast_read), read status register (rdsr) or release from deep power-down, read device identification and read electronic signature (res) instruction, the shifted-in instruction sequence is followed by a data-out sequence. chip select ( s ) can be driven high after any bit of the data-out sequence is being shifted out. in the case of a page program (pp), sector erase (se), bulk erase (be), write status r egister (wrsr), write enable (wren), write disable (wrdi) or deep power-down (dp) instruction, chip select ( s ) must be driven high exactly at a byte boundary, otherwise the inst ruction is rejected, and is not executed. that is, chip select ( s ) must driven high when the number of clock pulses after chip select ( s ) being driven low is an exact multiple of eight. all attempts to access the memory array during a write status register cycle, program cycle or erase cycle are ignored, and the internal write status regi ster cycle, program cycle or erase cycle continues unaffected. table 3. instruction set instruction description one-byte instruction code address bytes dummy bytes data bytes wren write enable 0000 0110 06h 0 0 0 wrdi write disable 0000 0100 04h 0 0 0 rdsr read status register 0000 0101 05h 0 0 1 to wrsr write status register 0000 0001 01h 0 0 1 read read data bytes 0000 0011 03h 3 0 1 to fast_read read data bytes at higher speed 0000 1011 0bh 3 1 1 to pp page program 0000 0010 02h 3 0 1 to 256 se sector erase 1101 1000 d8h 3 0 0 be bulk erase 1100 0111 c7h 0 0 0 dp deep power-down 1011 1001 b9h 0 0 0 rdid read device identificati on 1001 1111 9fh 0 0 1 to 3 release from deep power-down, and read electronic signature 0 3 1 to res release from deep power-down 1010 1011 abh 0 0 0
a25l80p preliminary (may 2005, version 0.0) 9 amic technology corp. write enable (wren) the write enable (wren) instruct ion (figure 4.) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), sector erase (se), bulk erase (be) and write status register (wrsr) instruction. the write enable (wren) instru ction is entered by driving chip select ( s ) low, sending the instruction code, and then driving chip select ( s ) high. figure 4. write enable (wren) instruction sequence s c d q high impedance instruction 01 23 45 67 write disable (wrdi) the write disable (wrdi) instruct ion (figure 5.) resets the write enable latch (wel) bit. the write disable (wrdi) instructi on is entered by driving chip select ( s ) low, sending the instruct ion code, and then driving chip the write enable latch (wel) bit is reset under the following conditions: power-up write disable (wrdi) instruction completion write status register (wrs r) instruction completion page program (pp) instruction completion sector erase (se) instruction completion bulk erase (be) instruction completion figure 5. write disable (wrdi) instruction sequence s c d q high impedance instruction 01 23 45 67
a25l80p preliminary (may 2005, version 0.0) 10 amic technology corp. read status register (rdsr) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a program, eras e or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instructi on to the device. it is also possible to read the status regi ster continuously, as shown in figure 6. table 4. status register format srwd 0 0 bp2 bp1 bp0 wel wip status register write protect block protect bits write enable latch bit write in progress bit b0 b7 the status and control bits of the status register are as follows: wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. wel bit. the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no writ e status register, program or erase instruction is accepted. bp2, bp1, bp0 bits. the block protect (bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and er ase instructions. these bits are written with the write status register (wrsr) instruction. when one or both of the block pr otect (bp2, bp1, bp0) bits is set to 1, the relevant memory area (as defined in table 1.) becomes protected against p age program (pp) and sector erase (se) instructions. the block protect (bp2, bp1, bp0) bits can be written provided that the hardware protected mode has not been set. the bulk erase ( be) instruction is executed if, and only if, both block protect (bp2, bp1, bp0) bits are 0. srwd bit. the status register writ e disable (srwd) bit is operated in conjunction with the write protect ( w ) signal. the status register write disable (srwd) bit and write protect ( w ) signal allow the device to be put in the hardware protected mode (when the stat us register write disable (srwd) bit is set to 1, and write protect ( w ) is driven low). in this mode, the non-volatile bits of the status register (srwd, bp2, bp1, bp0) become r ead-only bits and the write status register (wrsr) instru ction is no longer accepted for execution. figure 6. read status register (rdsr) instruction sequence and data-out sequence 0 1 2 3 4 5 6 7 810 91112 13 14 15 msb msb status register out status register out high impedance instruction 012345 6 7 0 1 2 3 4 5 6 77 s c d q
a25l80p preliminary (may 2005, version 0.0) 11 amic technology corp. write status register (wrsr) the write status register (w rsr) instruction allows new values to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrs r) instruction is entered by driving chip select ( s ) low, followed by the instruction code and the data byte on serial data input (d). the instruction sequence is sh own in figure 7. the write status register (wrsr) instruct ion has no effect on b6, b5, b1 and b0 of the status register. b6 and b5 are always read as 0. chip select ( s ) must be driven high after the eighth bit of the data byte has been latched in. if not, the write st atus register (wrsr) instruction is not executed. as soon as chip select ( s ) is driven high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp2, bp1, bp0) bits, to define the size of the area t hat is to be treated as read-only, as defined in table 1. the wr ite status register (wrsr) instruction also allows the user to set or reset the status register write disable (srwd) bit in accordance with the write protect ( w ) signal. the status register write disable (srwd) bit and write protect ( w ) signal allow the device to be put in the hardware prot ected mode (hpm). the write status register (wrsr) instru ction is not executed once the hardware protected mode (hpm) is entered. figure 7. write status register (wrsr) instruction sequence 11 12 13 14 15 status register in high impedance instruction s c d q msb 810 9 012345 6 7 2 3 4 5 6 70 1
a25l80p preliminary (may 2005, version 0.0) 12 amic technology corp. table 5. protection modes memory content w signal srwd bit mode write protection of the status register protected area 1 unprotected area 1 1 0 0 0 1 1 software protected (spm) status register is writable (if the wren instruction has set the wel bit) the values in the srwd, bp2, bp1 and bp0 bits can be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions 0 1 hardware protected (hpm) status register is hardware write protected the values in the srwd, bp2, bp1 and bp0 bits cannot be changed protected against page program, sector erase and bulk erase ready to accept page program and sector erase instructions note: 1. as defined by the values in the block protect (bp2, bp1, bp0) bits of the status register, as shown in table 1. the protection features of the device are summarized in table 5. when the status register writ e disable (srwd) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instr uction, regardless of t he whether write protect ( w ) is driven high or low. when the status register writ e disable (srwd) bit of the status register is set to 1, two cases need to be considered, depending on the state of write protect ( w ): - if write protect ( w ) is driven high, it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. - if write protect (w) is driven low, it is not possible to write to the status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to writ e to the status register are rejected, and are not accepted for execution). as a consequence, all the data byte s in the memory area that are software protected (spm) by the block protect (bp2, bp1, bp0) bits of the status register, are also hardware protected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: - by setting the status regist er write disable (srwd) bit after driving write protect ( w ) low - or by driving write protect ( w ) low after setting the status register write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect ( w ) high. if write protect ( w ) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp2, bp1, bp0) bits of the status register, can be used.
a25l80p preliminary (may 2005, version 0.0) 13 amic technology corp. read data bytes (read) the device is first selected by driving chip select ( s ) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is shifted out on serial data output (q), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (c). the instruction sequence is shown in figure 8. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is terminated by driving chip select ( s ) high. chip select ( s ) can be driven high at any time during data output. any read data bytes (read) instruction, while an eras e, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 8. read data bytes (read) instruction sequence and data-out sequence s c d q instruction high impedance msb msb 810 9 012345 6 7 data out 1 data out 2 24-bit address 28 29 30 31 32 33 34 35 36 37 38 39 23 22 21 3 210 7 6 54 32 10 7
a25l80p preliminary (may 2005, version 0.0) 14 amic technology corp. read data bytes at higher speed (fast_read) the device is first selected by driving chip select ( s ) low. the instruction code for the read data bytes at higher speed (fast_read) instruction is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (c). then the memory contents, at that address, is sh ifted out on serial data output (q), each bit being shifted out, at a maximum frequency f c , during the falling edge of serial clock (c). the instruction sequence is shown in figure 9. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest ad dress is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes at higher speed (fast_read) instruction is terminated by driving chip select ( s ) high. chip select ( s ) can be driven high at any time during data output. any read data bytes at higher speed (fast_read) in- struction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 9. read data bytes at higher speed (fast_read) instruction sequence and data-out sequence instruction high impedance msb 810 9 012345 6 7 24-bit address 28 29 30 31 23 22 21 3 210 data out 1 data out 2 7 0 s c d q s c d q 32 33 34 35 36 37 38 39 654 1 7 3 40 41 42 43 44 45 46 47 20 dummy byte msb 0 msb 7 6 54 32 1 msb 7 6 54 32 1 0 note: address bits a23 to a20 are don?t care.
a25l80p preliminary (may 2005, version 0.0) 15 amic technology corp. page program (pp) the page program (pp) instruction allows bytes to be programmed in the memory (changing bits from 1 to 0). before it can be accepted, a write e nable (wren) instruction must previously have been executed. a fter the write enable (wren) instruction has been decoded, t he device sets the write enable latch (wel). the page program (pp) instruction is entered by driving chip select ( s ) low, followed by the instruction code, three address bytes and at least one data byte on serial data input (d). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyo nd the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). chip select ( s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 10. if more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within t he same page. if less than 256 data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. chip select ( s ) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select ( s ) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page which is protected by the block protect (bp2, bp1, bp0) bits (see table 2 and table 1) is not executed. figure 10. page program (pp) instruction sequence s c d instruction msb 810 9 012345 6 7 24-bit address 28 29 30 31 32 33 34 35 36 37 38 39 23 22 21 3 210 data byte 1 msb 7 6 54 32 1 0 3 data byte 256 55 53 54 52 data byte 3 51 50 49 48 47 46 45 44 43 42 41 40 data byte 2 0 msb 7 6 54 32 1 msb 7 6 54 32 1 0 msb 7 6 54 32 1 0 s c d 2072 2073 2074 2075 2076 2077 2078 2079 note: address bits a23 to a20 are don?t care.
a25l80p preliminary (may 2005, version 0.0) 16 amic technology corp. sector erase (se) the sector erase (se) instruction sets all bits to 1 (ffh). before it can be accepted, a wr ite enable (wren) instruction must previously have been exec uted. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the sector erase (se) instruct ion is entered by driving chip select ( s ) low, followed by the instructio n code on serial data input (d). chip select ( s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 11. chip select ( s ) must be driven high after the eighth bit of the instruction code has been latched in, ot herwise the sector erase instruction is not executed. as soon as chip select ( s ) is driven high, the self-timed sector erase cycle (whose duration is t be ) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed sector eras e cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the sector erase (se) instruct ion is executed only if all block protect (bp2, bp1, bp0) bits are 0. the sector erase (se) instruction is ignored if one, or more, sectors are protected. figure 11. sector erase (se) instruction sequence instruction msb 810 9 012345 6 7 24-bit address 28 29 30 31 23 s c d 22 21 3 210 0 23 notes: address bits a23 to a20 are don?t care.
a25l80p preliminary (may 2005, version 0.0) 17 amic technology corp. bulk erase (be) the bulk erase (be) instruction sets all bits to 1 (ffh). before it can be accepted, a write e nable (wren) instruction must previously have been executed. a fter the write enable (wren) instruction has been decoded, t he device sets the write enable latch (wel). the bulk erase (be) instructi on is entered by driving chip select ( s ) low, followed by the instructio n code on serial data input (d). chip select ( s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 12. chip select ( s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwis e the bulk erase instruction is not executed. as soon as chip select ( s ) is driven high, the self-timed bulk erase cycle (whose duration is t be ) is initiated. while the bulk erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed bulk erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the bulk erase (be) instruction is executed only if all block protect (bp2, bp1, bp0) bits are 0. the bulk erase (be) instruction is ignored if one, or more, sectors are protected. figure 12. bulk erase (be) instruction sequence s c d 1 2 3 4567 0 instruction notes: address bits a23 to a20 are don?t care.
a25l80p preliminary (may 2005, version 0.0) 18 amic technology corp. deep power-down (dp) executing the deep power-down (d p) instruction is the only way to put the device in the lowest consumption mode (the deep power-down mode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. driving chip select ( s ) high deselects the device, and puts the device in the standby mode (if there is no internal cycle currently in progress). but this mode is not the deep power-down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) instruction, to reduce the standby current (from i cc1 to i cc2 , as specified in dc characteristics table.). once the device has entered the deep power-down mode, all instructions are ignored exc ept the release from deep power-down and read electronic signature (res) instruction. this releases the device from this mode. the release from deep power-down and read electronic signature (res) instruction also allows the elec tronic signature of the device to be output on serial data output (q). the deep power-down mode automatically stops at power-down, and the device alwa ys powers-up in the standby mode. the deep power-down (dp) instruction is entered by driving chip select ( s ) low, followed by the instruction code on serial data input (d). chip select ( s ) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 13. chip select ( s ) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the deep power-down (dp) instruction is not executed. as soon as chip select ( s ) is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down (dp) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 13. deep power-down (dp) instruction sequence s c d 1 2 3 4567 0 instruction t dp stand-by mode deep power-down mode
a25l80p preliminary (may 2005, version 0.0) 19 amic technology corp. read device identification (rdid) the read identificatio n (rdid) instruction allows the 8-bit manufacturer identification code to be read, followed by two bytes of device identification. t he manufacturer identification is assigned by jedec, and has the value 37h, plus the continuation identific ation for amic technology. the device identification is assigned by the device manufacturer, and indicates the memory in the first bytes (02h), and the memory capacity of the device in the second byte (13h). any read identification (rdid) instruction while an erase, or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select ( s ) low. then, the 8-bit instruction code fo r the instruction is shifted in. this is followed by the 32-bit dev ice identification, stored in the memory, being shifted out on serial data output (q), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 14. the read identification (rdid) instruction is terminated by driving chip select ( s ) high at any time during data output. when chip select ( s ) is driven high, the device is put in the stand-by power mode. once in the stand-by power mode, the device waits to be selected, so t hat it can receive, decode and execute instructions. table. read identification (read_id) data-out sequence manufacture identification device identification continuation id manufacture id memory type memory capacity 7fh 37h 02h 13h figure 14. read identification (rdid) data-out sequence s c d q instruction high impedance continuation id 810 9 01 2 3 4 5 6 7 21 30 22 23 24 25 26 29 31 manufacture id memory type 15 14 13 10 9 8 23 22 21 18 17 16 31 30 29 26 25 24 13 15 14 16 17 18 33 32 34 38 37 39 device id 65 210 7
a25l80p preliminary (may 2005, version 0.0) 20 amic technology corp. release from deep power-down and read electronic signature (res) once the device has entered the deep power-down mode, all instructions are ignored exc ept the release from deep power-down and read electronic signature (res) instruction. executing this instruction take s the device out of the deep power-down mode. the instruction can also be used to read, on serial data output (q), the 8-bit electronic si gnature, whose value for the a25l80p is 13h . except while an erase, program or write status register cycle is in progress, the release from deep power-down and read electronic signature (res) instru ction always provides access to the 8-bit electronic signature of the device, and can be applied even if the deep power-down mode has not been entered. any release from deep power-down and read electronic signature (res) instruction whil e an erase, program or write status register cycle is in pr ogress, is not decoded, and has no effect on the cycle that is in progress. the device is first selected by driving chip select ( s ) low. the instruction code is followed by 3 dummy bytes, each bit being latched-in on serial data input (d) during the rising edge of serial clock (c). then, the 8-bi t electronic signature, stored in the memory, is shifted out on seri al data output (q), each bit being shifted out during the falling edge of serial clock (c). the instruction sequence is shown in figure 15. the release from deep power-down and read electronic signature (res) instruction is terminated by driving chip select ( s ) high after the electronic signature has been read at least once. sending additional clock cycles on serial clock (c), while chip select ( s ) is driven low, cause the electronic signature to be output repeatedly. when chip select ( s ) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the devic e was previously in the deep power-down mode, though, the transition to the standby power mode is delayed by t res2 , and chip select ( s ) must remain high for at least t res2 (max), as specified in ac characteristics table . once in the stand-by power mode, the device waits to be selected, so that it can re ceive, decode and execute instruc- tions. figure 15. release from deep power-down and read electronic signature (res) instruction sequence and data-out sequence s c d q instruction high impedance msb msb 810 9 012345 6 7 3 dummy butes 28 29 30 31 32 33 34 35 36 37 38 23 22 21 3 210 6 54 32 10 7 t res2 stand-by mode deep power-down mode note: the value of the 8-bit electroni c signature, for the a25l80p, is 13h.
a25l80p preliminary (may 2005, version 0.0) 21 amic technology corp. figure 16. release from deep power-down (res) instruction sequence s c d 1 2 3 4567 0 instruction t res1 high impedance q stand-by mode deep power-down mode driving chip select ( s ) high after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit electronic signature has been tr ansmitted for the first time (as shown in figure 16.), still insure s that the device is put into stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the devic e was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by t res1 , and chip select ( s ) must remain high for at least t res1 (max), as specified in ac characteristics table. once in the stand-by power mode, the device waits to be selected, so t hat it can receive, decode and execute instructions.
a25l80p preliminary (may 2005, version 0.0) 22 amic technology corp. power-up and power-down at power-up and power-down, t he device must not be selected (that is chip select ( s ) must follow the voltage applied on v cc ) until v cc reaches the correct value: - v cc (min) at power-up, and then for a further delay of t vsl - v ss at power-down usually a simple pull-up resistor on chip select ( s ) can be used to insure safe and proper power-up and power-down. to avoid data corruption and i nadvertent write operations during power up, a power on reset (por) circuit is included. the logic inside the device is held reset while v cc is less than the por threshold value, v wi ? all operations are disabled, and the device does not respond to any instruction. moreover, the device ignores all write enable (wren), page program (pp), sector erase ( se), bulk erase (be) and write status register (wrsr) instru ctions until a time delay of t puw has elapsed after the moment that v cc rises above the vwi threshold. however, the correct operation of t he device is not guaranteed if, by this time, v cc is still below v cc (min). no write status register, program or eras e instructions should be sent until the later of: - t puw after v cc passed the vwi threshold - t vsl afterv cc passed the v cc (min) level these values are specified in table 6. if the delay, t vs l , has elapsed, after v cc has risen above v cc (min), the device can be selected for read instructions even if the t puw delay is not yet fully elapsed. at power-up, the device is in the following state: - the device is in the sta ndby mode (not the deep power-down mode). - the write enable latch (wel) bit is reset. normal precautions must be taken for supply rail decoupling, to stabilize the v cc feed. each device in a system should have the v cc rail decoupled by a suitable capacitor close to the package pins. (generally, this capacitor is of the order of 0.1f). at power-down, when v cc drops from the operating voltage, to below the por threshold value, v wi , all operations are disabled and the device does not respond to any instruction. (the designer needs to be aware that if a power-down occurs while a write, program or erase cycl e is in progress, some data corruption can result.) figure 17-1. power-up timing time v cc v cc (max) v cc (min) t pu full device access
a25l80p preliminary (may 2005, version 0.0) 23 amic technology corp. figure 17-2. power-down and voltage drop time v cc v cc (max) v cc (min) t pd no device access allowed v cc (low) t pu device access allowed table 6. power-up timing and v wi threshold symbol parameter min. max. unit t vsl 1 v cc (min) to s low 10 s t puw 1 time delay to write instruction 1 10 ms v wi 1 write inhibit voltage 1 2 v note: 1. these parameters are characterized only. initial delivery state the device is delivered with the memory arra y erased: all bits are set to 1 (each byte contains ffh). the st atus register conta ins 00h (all status register bits are 0).
a25l80p preliminary (may 2005, version 0.0) 24 amic technology corp. absolute maximum ratings* storage temperature (tstg) . . . . . . . . . . . . . -65 c to + 150 c lead temperature during soldering (note 1) input and output voltage (with respect to ground) (vid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.6v to +4.0v supply voltage (vcc) . . . . . . . . . . . . . . . . . . . . . -0.6v to +4.0v electrostatic discharge voltage (human body model) (vesd) (note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2000v to 2000v notes: 1. compliant with jedec std j-std-020b (for small body, sn-pb or pb assembly). 2. jedec std jesd22-a114a (c1=100 pf, r1=1500 , r2=500 ) *comments stressing the device above the rating listed in the absolute maximum ratings" table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or an y other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the amic sure program and other rele vant quality documents. dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summari zed in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 7. operating conditions symbol parameter min. max. unit v cc supply voltage 2.7 3.6 v t a ambient operating temperature ?40 85 c table 8. data retention and endurance parameter condition min. max. unit erase/program cycles at 85c 100,000 cycles per sector data retention at 85c 20 years note: 1. this is preliminary data table 9. capacitance symbol parameter test condition min. max. unit c out output capacitance (q) v out = 0v 8 pf c in input capacitance (other pins) v in = 0v 6 pf note: sampled only, not 100% tested, at t a =25 c and a frequency of 33 mhz.
a25l80p preliminary (may 2005, version 0.0) 25 amic technology corp. table 10. dc characteristics symbol parameter test condition min. max. unit i li input leakage current 2 a i lo output leakage current 2 a i cc1 standby current s = v cc , v in = v ss or v cc 50 a i cc2 deep power-down current s = v cc , v in = v ss or v cc 10 a c= 0.1v cc / 0.9.v cc at 50mhz, q = open 8 ma i cc3 operating current (read) c= 0.1v cc / 0.9.v cc at 33mhz, q = open 4 ma i cc4 operating current (pp) s = v cc 15 ma i cc5 operating current (wrsr) s = v cc 15 ma i cc6 operating current (se) s = v cc 15 ma i cc7 operating current (be) s = v cc 15 ma v il input low voltage ?0.5 0.3v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6ma 0.4 v v oh output high voltage i oh = ?100a v cc ?0.2 v note: 1. this is preliminary data at 85c table 11. instruction times symbol alt. parameter min. typ. max. unit t w write status register cycle time 5 15 ms t pp page program cycle time 1.5 5 ms t se sector erase cycle time 1 3 s t be bulk erase cycle time 4.5 10 s note: 1. at 85 c 2. this is preliminary data table 12. ac measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2v cc to 0.8v cc v input timing reference voltages 0.3v cc to 0.7v cc v output timing reference voltages v cc / 2 v note: output hi-z is defined as the point where data out is no longer driven.
a25l80p preliminary (may 2005, version 0.0) 26 amic technology corp. figure 18. ac measurement i/o waveform 0.3v cc 0.5v cc 0.2v cc 0.7v cc 0.8v cc input levels input and output timing reference levels
a25l80p preliminary (may 2005, version 0.0) 27 amic technology corp. table 13. ac characteristics symbol alt. parameter min. 5 typ. max. 5 unit f c f c clock frequency for the following instructions: fast_read, pp, se, be, dp, res, rdid, wren, wrdi, rdsr, wrsr d.c. 50 mhz f r clock frequency for read instructions d.c. 33 mhz t ch 1 t clh clock high time 9 ns t cl 1 t cll clock low time 9 ns t clch 2 clock rise time 3 (peak to peak) 0.1 v/ns t chcl 2 clock fall time 3 (peak to peak) 0.1 v/ns t slch t css s active setup time (relative to c) 5 ns t chsl s not active hold ti me (relative to c) 5 ns t dvch t dsu data in setup time 5 ns t chdx t dh data in hold time 5 ns t chsh s active hold time (relative to c) 5 ns t shch s not active setup ti me (relative to c) 5 ns t shsl t csh s deselect time 100 ns t shqz 2 t dis output disable time 8 ns t clqv t v clock low to output valid 8 ns t clqx t ho output hold time 0 ns t hlch hold setup time (relative to c) 5 ns t chhh hold hold time (relative to c) 5 ns t hhch hold setup time (relative to c) 5 ns t chhl hold hold time (relative to c) 5 ns t hhqx 2 t lz hold to output low-z 8 ns t hlqz 2 t hz hold to output high-z 8 ns t whsl 4 write protect setup time 20 ns t shwl 4 write protect hold time 100 ns t dp 2 s high to deep power-down mode 3 s t res1 2 s high to standby mode without electronic signature read 30 s t res2 2 s high to standby mode with electronic signature read 30 s t w write status register cycle time 5 15 ms t pp page program cycle time 3 5 ms t se sector erase cycle time 1 3 s t be bulk erase cycle time 10 40 s note: 1. t ch + t cl must be greater than or equal to 1/ f c 2. value guaranteed by characterization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a wrsr instruction when srwd is set at 1.
a25l80p preliminary (may 2005, version 0.0) 28 amic technology corp. figure 19. serial input timing s c d tshsl high impedance q tslch tchsl tclch tshch tchdx tchsh tdvch tchcl lsb in msb in figure 20. write protect setup and hold timing during wrsr when srwd=1 high impedance tshsl tshwl s c d q w
a25l80p preliminary (may 2005, version 0.0) 29 amic technology corp. figure 21. hold timing s c d q hold thlqz thlch thhch tchhl tchhh thhqx figure 22. output timing s c d q addr.lsb in lsb out tclqv tclqv tch tclqx tclqx tcl tqlqh tqhql
a25l80p preliminary (may 2005, version 0.0) 30 amic technology corp. part numbering scheme a25 xxx x x xx x package mw = sop8 mf = sop16 device voltage l = 2.7-3.6v device version* device type a25 = amic serial flash 05 = 512 kbit 40 = 4 mbit 80 = 8 mbit 16 = 16 mbit device function p = page program & sector erase device density temperature* x package material blank: normal f: pb free x speed - mhz operating frequency * optional
a25l80p preliminary (may 2005, version 0.0) 31 amic technology corp. ordering information part no. speed (mhz) active read current typ. (ma) program/erase current typ. (ma) standby current typ. ( a) package a25l80pmw-50 8 pin sop a25l80pmw-50f 8 pin pb-free sop a25l80pmw-50u 8 pin sop a25l80pmw-50uf 50 8 15 50 8 pin pb-free sop a25l80pmf-50 16 pin sop a25l80pmf-50f 16 pin pb-free sop a25l80pmf-50u 16 pin sop a25l80pmf-50uf 50 8 15 50 16 pin pb-free sop -u is for industrial operat ing temperature range: -40 c ~ +85 c
a25l80p preliminary (may 2005, version 0.0) 32 amic technology corp. package information sop 8l (209mil) outline dimensions unit: mm e 4 1 e b 85 d a 2 a a 1 l e 1 0.25 gage plane seating plane c dimensions in mm symbol min nom max a 1.75 1.95 2.16 a 1 0.05 0.15 0.25 a 2 1.70 1.80 1.91 b 0.35 0.42 0.48 c 0.19 0.20 0.25 d 5.13 5.23 5.33 e 7.70 7.90 8.10 e 1 5.18 5.28 5.38 e 1.27 bsc l 0.50 0.65 0.80 0 - 8 notes: maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads
a25l80p preliminary (may 2005, version 0.0) 33 amic technology corp. package information sop 16l (300mil) outline dimensions unit: inch e 8 1 16 9 a a 1 l seating plane h 0.050 typ. 0.016 typ. d d 0.004max. 0.008 typ. 0.02 x 45 dimensions in inch symbol min max a 0.093 0.104 a 1 0.004 0.012 d 0.398 0.413 e 0.291 0.299 h 0.394 0.419 l 0.016 0.050 0 8 notes: 1. dimensions ?d? does not include mold flash, protrusions or gate burrs. 2. dimensions ?e? does not include interlead flash, or protrusions.

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